Methods of Manufacturing Semiconductor devices Having Buried Bit Lines

ABSTRACT

A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

PRIORITY CLAIM AND CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.11/240,544, filed on Sep. 30, 2005 and claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2004-0107993, filed on Dec. 17,2004, in the Korean Intellectual Property Office, the disclosures ofboth are incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods ofmanufacturing semiconductor devices, and more particularly tosemiconductor devices having buried bit lines and methods ofmanufacturing semiconductor devices having buried bit lines.

BACKGROUND

In a semiconductor device such as a non-volatile memory device havingburied bit lines, an impurity may be selectively doped in upper portionsof a semiconductor substrate to form buried bit lines in the substratewhich are spaced uniformly from one another. A buried bit line formeddirectly in a semiconductor substrate may require minimal space.

FIG. 1 is a plan view of a conventional NOR device with a SONOSstructure having buried bit lines. Bit lines 12 are formed in upperportions of a semiconductor substrate 10 doped with an impurity of afirst conductivity type, e.g., a P-type impurity, by selectively dopingthe substrate with an impurity, e.g., an N-type impurity, of a secondconductivity type opposite to that of the semiconductor substrate 10.Bit lines 12 may have a higher net doping concentration than substrate10 and may be spaced uniformly from one another while extending in afirst direction (e.g. the Y-axis direction indicated in FIG. 1). The bitlines 12 may have a stripe pattern. The word lines 14 may be formed atright angles to the bit lines 12. The word lines 14 may be spaceduniformly from one another and may cover portions of the semiconductorsubstrate 10 and the bit lines 12. The word lines 14 may be shaped asstripes and may cover channel regions 16 formed in the upper portions ofthe semiconductor substrate 10 and source/drain regions 18 formed in thebit lines 12. Bit line contacts 20 for external electrical connectionmay be formed at one end of the bit lines 12.

In some conventional semiconductor devices having buried bit lines,device isolation of the bit lines 12 is performed by PN junctionsbetween the bit lines and the semiconductor substrate 10, which haveopposite conductivity types. However, as semiconductor devices areminiaturized, punch-through (i.e. a breakdown due to overlappingjunction depletion regions) may occur at the PN junction, resulting in aloss of device isolation. That is, as the distance between adjacent bitlines is reduced in an effort to make devices smaller, the effectivenessof PN junction isolation as a means to isolate adjacent devices may bereduced.

Furthermore, with the high integration of semiconductor devices, thegate channel length is decreased. This may result in several problems,such as a short channel effects, microscopic pattern formation, andrestricted operating speed. In particular, various short channel effectsmay become a serious problem. For example, an increased electric fieldaround the drain region may cause punch-through that penetrates to thepotential barrier around a source region. Also, thermo-electrons maycause avalanche breakdown, and a vertical electric field may decreasethe vertical mobility of carriers.

SUMMARY

According to some embodiments of the invention, a semiconductor deviceincludes a semiconductor substrate having a first conductivity type, apair of bit lines extending in a first direction and doped with animpurity of a second conductivity type opposite to the firstconductivity type and spaced from one another in an upper portion of thesemiconductor substrate, a first line formed between the pair of bitlines having a plurality of alternating recessed device isolationregions and channel regions, with each of the channel regions contactingeach bit line of the at least one pair of bit lines, and word linesformed at right angles to the first lines and covering the channelregions.

In some embodiments of the invention, the first conductivity type isP-type and the second conductivity type is N-type.

In some embodiments of the invention, the recessed isolation regions mayisolate the at least one pair of bit lines from one another. Therecessed isolation regions may further isolate adjacent pairs of channelregions from one another.

In some embodiments of the invention, each of the channel regionsincludes an upper surface and a pair of opposing sidewalls. An ONO layeris formed on the sidewalls and on the upper surface of the channelregion, and a gate electrode is formed on the ONO layer. In someembodiments, the ONO layer and the gate electrode layer extend onto theupper surfaces of adjacent bit lines. The device isolation regions maybe filled with HDP oxide and may extend into the substrate.

Some embodiments of the invention include an insulating layer formed inthe recess regions and covering surface portions of each of the bitlines. A bit line contact may be formed through the insulating layer forproviding electrical contact to at least one of the bit lines.

In some embodiments of the invention, a filling layer is formedpartially filling each of the recess regions, and the ONO layer is atleast partially formed on the filling layer. The filling layer mayinclude an HDP oxide, TEOS, USG or a PECVD oxide.

Some embodiments of the invention provide a unit cell of a semiconductormemory device having a semiconductor substrate, a pair of bit linesdoped with an impurity having conductivity type opposite to that of thesubstrate and spaced from one another in the upper portion of thesemiconductor substrate, a channel region between the pair of bit lines,the channel region having an upper surface and a pair of opposing sidesurfaces, a pair of recess regions adjacent the opposing side surfacesof the channel region and separating the pair of bit lines on eitherside of the channel region, an ONO layer formed on the bit lines and theupper and side surfaces of the channel region, and a gate electrodeformed on the ONO layer above the upper surface and side surfaces of thechannel region.

In some embodiments, the unit cell may have an insulating layer formedin the recess regions and covering surface portions of each of the bitlines, and a bit line contact extending through the insulating layer forproviding electrical contact to at least one of the bit lines.

Some embodiments of the invention include a filling layer partiallyfilling each of the recess regions, wherein the ONO layer is at leastpartially formed on the filling layer. The filling layer may include anHDP oxide, TEOS, USG or a PECVD oxide.

According to some embodiments of the invention, methods of forming asemiconductor device include forming a plurality of bit lines spacedfrom one another and extending in a first direction in an upper portionof a semiconductor substrate having a first conductivity type, byselectively doping an upper portion of the substrate with an impurity ofa second conductivity type that is opposite to first conductivity type.A mask layer is formed on a surface of the semiconductor substrate abovethe upper portion of the substrate, and a plurality of spaced apartrecess regions are formed between the bit lines. The recess regions mayextend through the mask layer and into the substrate.

Methods according to the invention further include depositing a firstfilling layer in the recess regions, removing the mask layer to exposethe surface of the semiconductor substrate, partially removing the firstfilling layer from the semiconductor substrate, to form a second fillinglayer exposing sidewalls of the recess regions. The first filling layermay include an HDP oxide, TEOS, USG or a PECVD oxide. An ONO layer isformed on the surface of the semiconductor substrate including thesidewalls of the recess regions and the second filling layer, and a gateelectrode layer is formed on the ONO layer over the sidewalls of therecess regions extending between adjacent pairs of bit lines.Accordingly, in some embodiments, the channel width may be determined bythe height of the second filling layer.

In some embodiments, forming a plurality of spaced apart recess regionsdefines a plurality of channel regions extending between adjacent pairsof bit lines. The ONO layer covers the plurality of channel regions.

In some embodiments, forming the recess regions includes forming aphotoresist pattern for defining the recess regions on the mask layer,and partially removing the mask layer and the semiconductor substrate inthe shape of the photoresist pattern to form the recess regions.

In some embodiments, the ONO layer may serves as an etch stop layer whenforming the gate electrode.

Some embodiments of the invention further include forming an insulatinglayer in the recess regions and extending onto the bit lines, andforming a bit line contact in the insulating layer for an externalelectrical connection to one end of the bit line.

In some embodiments according to the invention, methods of forming asemiconductor device include forming bit lines spaced from one anotherand extending in a first direction in an upper portion of asemiconductor substrate of a first conductivity type by selectivelydoping portions of the upper portion of the substrate with an impurityof a second conductivity type that is opposite to first conductivitytype, forming a plurality of spaced apart recess regions extendingbetween the bit lines and into the substrate, each of the recess regionshaving at least a pair of opposing sidewalls extending between a pair ofadjacent bit lines, partially filling the recess region with a fillinglayer, blanket coating an ONO layer on the surface of the semiconductorsubstrate including the filling layer and sidewalls of the recessregions, and forming a gate electrode layer on the ONO layer over theopposing sidewalls of the recess regions.

Some embodiments of the invention may provide semiconductor devices withan increased channel area and/or a higher device density by overcomingthe restrictions of using PN junctions for device isolation betweenburied bit lines.

Some embodiments of the invention may provide methods of manufacturing asemiconductor device with an increased channel area and/or a higherdevice density by overcoming the restrictions of using PN junctions fordevice isolation between buried bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a plan view of a conventional NOR device with a SONOSstructure having buried bit lines;

FIG. 2A is a perspective view of a non-volatile memory device with aSONOS structure having buried bit lines according to embodiments of theinvention;

FIGS. 2B through 2E are sectional views respectively taken along lines2B-2B, 2C-2C, 2D-2D and 2E-2E of FIG. 2A; and

FIGS. 3 through 9 are perspective views showing methods of manufacturinga non-volatile memory device with a SONOS structure having buried bitlines according to embodiments of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity. It will beunderstood that when an element or layer is referred to as being “on” or“connected to” another element or layer, it can be directly on ordirectly connected to the other element or layer or intervening elementsor layers may be present.

Like reference numerals refer to like elements throughout. As usedherein the term “and/or” includes any and all combinations of one ormore of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components or layers, theseelements, components or layers should not be limited by these terms.These terms are only used to distinguish one element, component or layerfrom another element, component or layer. Thus, a first element,component or layer discussed below could be termed a second element,component or layer without departing from the teachings of the presentinvention.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly. It will also beappreciated by those of skill in the art that references to a structureor feature that is disposed “adjacent” another feature may have portionsthat overlap or underlie the adjacent feature.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, elements or components, but do not precludethe presence or addition of one or more other features, elements orcomponents.

Embodiments of the invention are described herein with reference tocross-sectional, perspective, and/or plan view illustrations that areschematic illustrations of idealized embodiments of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an etched region illustrated or described asa rectangle will, typically, have rounded or curved features. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the precise shape of a region of adevice and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

The embodiments are described with reference to a non-volatile memorydevice with a SONOS structure. However, the present invention is notlimited to a non-volatile memory device with a SONOS structure, and canbe employed in various structures by those skilled in the art.

FIG. 2A is a perspective view of a non-volatile memory device with aSONOS structure having a buried bit line 102 according to embodiments ofthe invention. FIGS. 2B through 2E are sectional views respectivelytaken along lines 2B-2B, 2C-2C, 2D-2D and 2E-2E of FIG. 2A.

Referring to the embodiments of FIGS. 2A through 2E, a semiconductormemory device 101 having a plurality of unit memory cells isillustrated. Upper portions of a semiconductor substrate 100 are dopedwith an impurity of a first conductivity type, e.g., a P-type impurity,and contain the bit lines 102 doped with an impurity, e.g., an N-typeimpurity, of a second conductivity type opposite to that of thesemiconductor substrate. The substrate 100 may comprise silicon,silicon-on-insulator (SOI) or any other suitable semiconductorsubstrate. The bit lines 102 may be spaced uniformly from one anotherand may extend in a first direction (e.g. Y-axis direction as indicatedin FIG. 2A). In some embodiments, the net doping concentration of thebit lines 102 may exceed the net doping concentration of the substrate100. As illustrated in FIG. 2C, the semiconductor substrate 100 may bepatterned to form a plurality of spaced apart recess regions 108. Therecess regions 108, which may be filled with device isolating layers(144 of FIG. 9), are formed between the bit lines 102. As describedbelow, the device isolating layers 144 may reduce the possibility of anelectrical short between adjacent channel regions 114 and/or betweenadjacent bit lines 102.

As illustrated in FIG. 2B, regions of the bit lines adjacent the channelregions 114 form source/drain regions 116 of the unit cells of thesemiconductor memory device.

As illustrated in FIG. 2D, channel regions 114 may be formed along thefirst direction (the Y-axis direction) between the recess regions 108.By doing so, a recess region 108 and an adjacent channel region 114 forma pair that is repeated along the first direction (Y-axis direction).The channel regions 114 extend between adjacent bit lines 102. Asfurther illustrated in FIG. 2D, the vertical dimensions of channelregion 114 extend between the top of a second filling layer 112 at thebottom of the recess region 108 and the upper surface of thesemiconductor substrate 100. Accordingly, each channel region 114 of thesemiconductor device is shaped as a fin having opposing sidewalls 114Aand an upper surface 114B as illustrated in FIG. 2D.

The channel regions 114 are covered with word lines 150 which may extendalong a second direction (e.g. the X-axis direction), at right angles tothe first direction (the Y-axis direction). The word line 150 includes agate electrode layer 140, and an ONO layer 138 including a first oxidelayer 132, a nitride layer 134 and a second oxide layer 136. In someembodiments, the word line 150 also covers the source/drain regions 116formed in the bit line 102 between the channel regions 114 along thesecond direction (the X-axis direction). In other words, in someembodiments, the word line 150 covers both the channel region 114 andthe source/drain regions 116. As shown in FIG. 2B, the gate electrodelayer 140 may be formed on the ONO layer 138 over both the sidewalls114A and the upper surface of the channel region 114B. Also, asillustrated in FIG. 2E, the gate electrode layer 140 may be formed overthe upper surface of the source/drain regions 116 on which the ONO layer138 is also formed.

FIGS. 3 through 9 are perspective views showing methods of manufacturingnon-volatile memory devices with an ONO structure having a buried bitline 102 according to an embodiments of the invention.

Referring to the embodiments of FIG. 3, upper portions of asemiconductor substrate 100 may be doped with an impurity of a firstconductivity type, e.g., a P-type impurity, and the bit lines 102 may bedoped with an impurity, e.g., an N-type impurity of a secondconductivity type opposite to that of the semiconductor substrate 100.In some embodiments, the net doping concentration of bit lines 102 mayexceed the net doping concentration of substrate 100. A first mask layer104 may be formed on the surface of the semiconductor substrate 100where the bit lines 102 are located. A second mask layer 106 fordefining a plurality of recess regions may be formed by a standardmethod on the first mask layer 104. In some embodiments, the first masklayer 104 may be a silicon oxide layer, and the second mask layer 106may be a silicon nitride layer.

Referring to FIG. 4, the second mask layer 106 may be removed by astandard method using H₃PO₄ or similar. Thereafter, using the first masklayer 104 as an etch mask, the semiconductor substrate 100 may bepartially etched in the shape of the second mask layer 106, therebyforming a plurality of recess regions 108. In order to obtain a desiredetch profile, the recess regions 108 may be formed by a dry etchingtechnique such as plasma etching or reactive ion etching.

In some cases, the recess regions 108 may be formed by other methods.For example, in some embodiments, a photoresist pattern (not shown) fordefining the recess regions may be formed on the first mask layer 104.Then, portions of the first mask layer 104 and the semiconductorsubstrate 100 are partially removed in the shape of the photoresistpattern. However, since the photoresist pattern may be deformed duringetching, the first mask layer 104 may be used as an etch mask.

Referring to the embodiments of FIG. 5, the recess regions 108 may befilled with a first filling layer 110. In some embodiments, the firstfilling layer 110 may be a USG (Undoped Silicate Glass) layer, an HDP(High Density Plasma) oxide layer, a TEOS (tetraethylorthosilicate)layer formed using PECVD (Plasma Enhanced Chemical Vapor Deposition), anoxide layer formed using PECVD, or an insulating layer formed using acombination of any of such methods. In some embodiments, due to thedense structure of HDP oxides, an HDP oxide layer may be suitable forfilling the recess regions 108.

HDP CVD is a combination of CVD and etching by sputtering in which achamber is supplied with both a deposition gas for depositing a materiallayer and a sputtering gas for etching the deposited material layer bysputtering. Accordingly, SiH₄ and O₂ are supplied into a chamber asdeposition gases, and an inert gas (e.g., Ar) is supplied into thechamber as a sputtering gas. The deposition gas and the sputtering gasare partially ionized by a plasma which is created within the chamberusing a high frequency electric field. Because a wafer chuck (e.g., anelectrostatic chuck) which holds the substrate in the chamber issupplied with a biased high frequency electric field, the ionizeddeposition gas ions and ionized sputtering gas ions are acceleratedtoward the surface of the substrate. The accelerated deposition gas ionsform a silicon oxide layer, and the accelerated sputtering gas ionssputter the silicon oxide layer. As a result, the HDP oxide layerconstituting the first filling layer 110 has a high density and good gapfilling characteristics.

Referring to the embodiments of FIG. 6, the first layer 104 and portionsof the first filling layer 110 are removed to expose the upper surfaceof the semiconductor substrate 100, which may then be planarized.Planarization may be performed using Chemical Mechanical polishing (CMP)or etchback. When planarization is finished, the upper surface 114B ofthe channel region 114 located in the semiconductor substrate 100between the first filling layers 110 and the source/drain regions 116disposed adjacent the channel regions 114 are exposed. The source/drainregions 116 refer to regions within the bit lines 102 adjacent thechannel regions 114.

Referring to the embodiments of FIG. 7, the first filling layer 110formed in the semiconductor substrate 100 is partially removed to formrecess regions 108. Stated differently, by partially removing portionsof first filling layer 110, a second filling layer 112 is formed thatexposes the sidewalls 114A of the channel region 114. The amount removedfrom the first filling layer 110 may determine the channel width of thesemiconductor device according to some embodiments of the invention.When the etched depth is small, the width of the channel region 114 maybe decreased. Therefore, the amount of material removed from firstfilling layer 110 is selected based on the desired channel width of thechannel regions 114. The first filling layer 110 may be removed bydiluted HF, diluted NH₄F or Buffered Oxide Etchant (BOE) which is amixture of HF and deionized solution. The channel length of the channelregions 114 is determined by the spacing of adjacent bit lines 102.

Referring to the embodiments of FIG. 8, an ONO layer 138, which in someembodiments may have a uniform thickness, is formed over the surface ofthe semiconductor substrate 100 and the second filling layer 112 via ablanket method. Thereafter, a gate electrode layer 140 is formed tocover the ONO layer 138 over sidewalls 114A, of the channel region 114,as well as the upper surface 114B of channel region 114. The gateelectrode layer 140 may be patterned using the ONO layer 138 as an etchstop layer. More specifically, the gate electrode layer 140 may beformed by depositing a gate electrode material layer on the wholesurface of the ONO layer 138. Then, a photoresist pattern for definingthe gate electrode layer 140 is formed on the gate electrode materiallayer. The gate electrode layer 140 may be formed by etching the gateelectrode material layer using the photoresist layer as an etch mask. Insome embodiments, the ONO layer 138 may serve as an etch stop layer thatprevents etching of the underlying material.

Referring to the embodiments of FIG. 9, after forming the gate electrodelayer 140, an interlayer insulating layer 142 may be formed on thesurface of the semiconductor substrate 100 and the gate electrode layer140. The interlayer insulating material may include an HDP oxide. A bitline contact 146 may be formed in the second interlayer insulating layer142 for providing external electrical connection to one end of a bitline 102. In some embodiments, the interlayer insulating layer 142 mayfill the recess regions 108, thereby simultaneously isolating adjacentword lines 150 and adjacent bit lines 102. The device isolating layer144 may be formed in the recess regions 108 to reduce the possibility ofelectrical shorts between adjacent channel regions 114 and/or adjacentbit lines 102.

Embodiments of the invention provide a semiconductor device havingburied bit lines and methods of manufacturing the same. A deviceisolating layer for isolating adjacent buried bit lines and channelregions is formed by recessing a semiconductor substrate, therebyisolating conductive regions from one another.

Furthermore, in some embodiments of the invention the device isolatinglayer may be formed by recessing the semiconductor substrate so thatfin-shaped channel regions are created, which may avoid or reduce theimpact of certain short channel effects.

Embodiments of the present invention have been disclosed herein and,although specific terms are employed, they are used and are to beinterpreted in a generic and descriptive sense only and not for purposeof limitation. Accordingly, it will be understood by those of ordinaryskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims. For example, a silicon oxide layermay be applied instead of ONO as the gate insulating layer.

1. A method of forming a semiconductor device, comprising: forming aplurality of bit lines spaced from one another and extending in a firstdirection in an upper portion of a semiconductor substrate having afirst conductivity type, by selectively doping an upper portion of thesubstrate with an impurity of a second conductivity type that isopposite to first conductivity type; forming a mask layer on a surfaceof the semiconductor substrate above the upper portion of the substrate;forming a plurality of spaced apart recess regions extending through themask layer and into the substrate between adjacent bit lines of theplurality of bit lines, each of the recess regions having a pair ofopposing sidewalls oriented in parallel to a pair of adjacent bit linesand a pair of opposing sidewalls extending between a pair of adjacentbit lines; depositing a first filling layer in the recess region;removing the mask layer to expose the surface of the semiconductorsubstrate; partially removing the first filling layer from thesemiconductor substrate, to form a second filling layer exposingsidewalls of the recess regions; forming an ONO layer on the surface ofthe semiconductor substrate including the sidewalls of the recessregions and the second filling layer; and forming a gate electrode layeron the ONO layer over the sidewalls of the recess regions extendingbetween adjacent pairs of bit lines.
 2. The method of claim 1, whereinthe first conductivity type is P-type and the second conductivity typeis N-type.
 3. The method of claim 1, wherein forming a plurality ofspaced apart recess regions comprises defining a plurality of channelregions extending between adjacent pairs of bit lines.
 4. The method ofclaim 3, wherein the ONO layer covers the plurality of channel regions.5. The method of claim 1, wherein forming the recess region comprises:forming a photoresist pattern for defining the recess regions on themask layer; and partially removing the mask layer and the semiconductorsubstrate in the shape of the photoresist pattern to form the recessregion.
 6. The method of claim 1, wherein the first filling layercomprises an HDP oxide layer, TEOS, USG or a PECVD oxide.
 7. The methodof claim 1, wherein a height of the sidewalls of the semiconductorsubstrate exposed by partially removing the first filling layerdetermines a width of the channel region.
 8. The method of claim 1,wherein forming the gate electrode layer comprises using the ONO layeras an etch stop layer.
 9. The method of claim 1, further comprising:forming an insulating layer in the recess regions, the insulating layerextending above the bit lines adjacent to the recess regions; andforming a bit line contact in the insulating layer for providing anexternal electrical connection to one of the plurality of bit lines. 10.A method of forming a semiconductor device, comprising: forming aplurality of bit lines spaced from one another and extending in a firstdirection in an upper portion of a semiconductor substrate of a firstconductivity type by selectively doping portions of the upper portion ofthe substrate with an impurity of a second conductivity type that isopposite to first conductivity type; forming a plurality of spaced apartrecess regions extending between adjacent pairs of the plurality of bitlines and into the substrate, each of the recess regions having at leasta pair of opposing sidewalls extending between a pair of adjacent bitlines; partially filling the recess region with a filling layer; formingan ONO layer on the surface of the semiconductor substrate including thefilling layer and sidewalls of the recess regions; and forming a gateelectrode layer on the ONO layer over the opposing sidewalls of therecess regions.
 11. The method of claim 10, wherein the firstconductivity type is P-type and the second conductivity type is N-type.12. The method of claim 10, wherein forming a plurality of spaced apartrecess regions defines a plurality of channel regions extending betweenadjacent pairs of bit lines.
 13. The method of claim 12, wherein the ONOlayer covers the plurality of channel regions.
 14. The method of claim10, wherein the filling layer comprises an HDP oxide, TEOS, USG or aPECVD oxide.
 15. The method of claim 10, further comprising: forming aninsulating layer in the recess regions, the insulating layer extendingabove the bit lines adjacent to the recess regions; and forming a bitline contact in the insulating layer for providing an externalelectrical connection to one of the plurality of bit lines.